ͻ
 MPU Z380 
ͼ
[ த. 砫   11,10,9,8,7 ].

(C) WLODEK BLACK.

	㯯  䬥⨪ ᭮ 祭
	 㯯  ࠢ 業ࠫ ஬.

 :

			਩

CPLW		HL <- NOT HL	  HL, 㯠饩
CPLW HL				 ஫ 16-ࠧ來 -
				.

NEGW		HL <- 0-HL	  祭  HL
NEGW HL

EXTS		L <- A
EXTS A		H <- 00, ᫨ D7  = 0;
		H <- #FF,  ᫨ -"- = 1

				७ 8-ࠧ來 祭
	  16 ( 32   ० " ᫮")
	  ७ᥭ १  HL.  ࠧ -
	ࠧ  祭  ࠧ冷 ᫮.

EXTSW		HLz <- #0000  H(7)=0;
EXTSW HL	HLz <- #FFFF  H(7)=1

				७ 16-ࠧ來  -
				 HL  32   ⮬ .

SLP		Sleep		ॢ 奬  
	० 筮 ⠭. ४頥  ⠪-
	⮢ ᮢ ஥ 筨;   ⪫-
	砥  設   ࠢ; 設  ॢ-
	  ﭨ .1   ⮪; १  ᭨-
	 ࣮ॡ.   Sleep  ᮬ, -
	뢠 ᪨㥬  ᪨㥬  ᮬ   -
	 ⥬ 設. ᫨ 室  Sleep 饭  (? -
	  ࠧࠫ, !),  SLP 믮  HALT.

DI n	IER(i) <- 0  ᮮ⢥⢨  ⠬ n.
	SR(5)  <- 0 ᫨ n(0)=1.
	ᥭ  ᪨ ⮢  饭 뢠  ॣ
	ࠧ襭 뢠.  4    (0...3)
	 ॣ IER  (஡ 㤥 ᢥ饭   祭
	० 뢠).

EI n	IER(i) <- 1 -"-   筮  ࠧ襭 뢠.
	SR(5)  <- 1 -"-.

IM 3			  祭 3- ० 뢠.

LDCTL SR,A	SR(31-24) <- A	樠 ॣ ࠢ-
		SR(23-16) <- A	 祭 .
		SR(15-8)  <- A

LDCTL SR,n	Load Control	  - ⠭⮩.
		SR(31-24) <- n
		SR(23-16) <- n
		SR(15-8)  <- n

LDCTL HL,SR	HL(15-0) <- SR(15-0)	⥭ ॣ ࠢ-
		   HL.  ० " ᫮" 
		32 .

LDCTL SR,HL	SR(15-8) <- HL(15-8)	㧪 ॣ ࠢ-
		SR(0)    <- HL(0)	 祭  HL.
		SR(31-24)<- HL(15-8)
		SR(23-16)<- HL(15-8)
		 ० " ᫮":
		SR(31-16)<- HL(31-16)

LDCTL A,v	A <- v		⥭ 8-⮢ 㯯 ॣ
			ࠢ SR  . ("v" - 
			 㯯 YSR, XSR  DSR).

LDCTL v,A	v <- A		㧪 8-⮢ 㯯 ॣ-
			 ࠢ SR 祭  -
			.

LDCTL v,n	v <- n		  ⠭⮩.

SET LCK		SR(1) <- 1	⠭ ஢ ᮢ
			 墠 ⥬ 設.

RESC LCK	SR(1) <- 0	 ஢ -"-.

SETC LW		SR(6) <- 1	⠭ ० " ᫮"

RESC LW		SR(6) <- 0	⬥ ० " ᫮".

BTEST		Bank Test	ᥭ  ⮢ ॣ-
		S <- SR(16)	 ࠢ  䫠.
		Z <- SR(24)
		V <- SR(0)
		C <- SR(8)

MTEST		Mode Test	 ,   㣨 ⠬ 
		S <- SR(7)	஢ન 㣨 ﭨ.
		Z <- SR(6)
		C <- SR(1)

[ த ᫥ ].
