                 SGS-THOMPSON  Microelectronics                September 1993

                   TELETEXT PROCESSOR SDA5243
                  
FEATURES:

. AUTOMATIC SELECTION OF UP TO SEVEN NATIONAL LANGUAGES
. FOUR SIMULTANEOUS PAGE REQUESTS
. DISPLAY OF THE 25TH STATUS ROW
. MICROPROCESSOR CONTROL VIA AN I2C BUS (SLAVE ADDRESS 0010001 R/W)
. DATA ACQUISITION AVAILABLE FROM LINES 2 TO 22 OR FROM A COMPLETE FIELD.
. DIRECT INTERFACE TO A STATIC RAM OF UP TO 8kBYTES
. HIGH QUALITY DISPLAY USING A CHARACTER MATRIX OF 12 x 10 DOTS.. SINGLE + 5V 
  SUPPLY VOLTAGE
. ON-CHIP MASK PROGRAMMABLE ROM CHARACTER GENERATORS
. NMOSH2 PROCESS

          Ŀ
VDD               40  A10
A11      ܳ2          39  A9 
A12      ܳ3          38  A8 
OE       ܳ4          37  A7 
WE       ܳ5          36  A6 
TTD      ܳ6          35  A5 
TTC      ܳ7          34  A4 
ODD/EVEN ܳ8          33  A3 
F6       ܳ9          32  A2 
VCS      ܳ10         31  A1 
SAND     ܳ11         30  A0 
TCS/SCS  ܳ12         29  D7 
R        ܳ13         28  D6 
G        ܳ14         27  D5 
B        ܳ15         26  D4 
COR      ܳ16         25  D3 
BLAN     ܳ17         24  D2 
Y        ܳ18         23  D1 
SCL      ܳ19         22  D0 
SDA      ܳ20         21  Vss
          

PIN DESCRIPTION
                                                                                                                                
Ŀ
Pin    Symbol        Function                Description                                                               
Ĵ
1      VDD             +5V                   Positive supply voltage                                                   
Ĵ
2,3,40 A11,A12,A10   Chapter address         Address selection outputs for 1 of 8 static RAM chapters each of 1 kBytes.
Ĵ
4      OE            Output enable           Active-low RAM output enable control signal.                              
Ĵ
5      WE            Write enable            Active-low RAM write enable control signal. It supports write-            
                                             cycles interleaved with read-cycles.                                      
Ĵ
6      TTD           Teletext data input     An A.C. coupled teletext data input supplied by the SAA5231 chip          
                                             is latched to VSS between 4 and 8 m s after each TV line.                 
Ĵ
7      TTC           Teletext clock input    A 6.9375MHz clock signal, supplied by the SAA5231 chip, is                
                                             internally A.C. coupled, clamped and buffered.                            
Ĵ
8      ODD/EVEN      Interlaced mode state   High for even numbered and low for odd-numbered frames. The               
                          output             value is valid 2 m s before the end of lines 311 and 624.                 
Ĵ
9      F6           Character display clock  The 6MHz clock signal, supplied by the SAA5231 chip is internally         
                           signal            A.C. coupled, clamped and buffered.                                       
Ĵ
10     VCS             Video composite       Active high VCS input.                                                    
                     synchronization input                                                                             
                           signal                                                                                      
Ĵ
11    SAND                Sandcastle         Three level output pulse to the SAA5231 device. Phase lock,               
                                             blanking signal, and color burst components are contained in this         
                                             signal.                                                                   
Ĵ
12    TCS/SCS      Input / output composite  Scan composite input signal (SCS) for the display synchronization         
                    synchronization signal   or Text composite sync. (TCS) output signal to the SAA5231. Both          
                                             signals are active low.                                                   
Ĵ
13,14,R G B         Red, green, blue         Character and background colors active-high open-drain outputs.           
 15                                                                                                                    
Ĵ
16    COR            Contrast reduction      Open-drain active-low output supporting optimal display of                
                                             characters in "mixed mode" operation.                                     
Ĵ
17    BLAN          Blanking signal output   Open-drain active high output for TV-image blanking in normal             
                                             and mixed-mode operation.                                                 
Ĵ
18     Y             Foreground output       Open-drain active-high output with foreground information. Can            
                                             be used for printer command.                                              
Ĵ
19    SCL            Serial clock            Microprocessor clock input via serial bus.                                
Ĵ
20    SDA          Serial data input/output  Open-drain microprocessor serial data input/output via serial bus.        
Ĵ
21    VSS            0 Volt                  Ground.                                                                   
Ĵ
22-29 D0-D7       Parallel data input/output Eight tri-state input/output for data read/write from/to an external      
                                             RAM.                                                                      
Ĵ
30-39 A0-A9          Address signals         Ten addresses output pins for accessing to individual Bytes of a          
                                             1 kByte chapter stored in an external Static RAM.                         



DESCRIPTION

The SDA5243 is a NMOSH2 integrated circuit which performs all the processing
of logical data within a 625 line system teletext decoder. It is designed to
operate in conjunction with at least two chips : the SAA5231 integrated chip
which extracts Teletext information embedded in a composite video signal and
up to eight kilobytes of static RAM memory which can be used to store a 
maximum of 8 pages of display data. A complete system also comprises a 
microprocessor controling the SDA5243 via a 2-wire serial bus. An on-chip ROM
memory contains the character sets. The SDA5243 performs automatic selection
of one of up to seven natural languages. Data bytes may be decoded in either
7-Bit plus parity or in full 8-Bit formats. The chip set also supports 
facilities for reception and display of higher-level protocol data.

APPLICATION NOTES ORGANIZATION OF A PAGE-MEMORY

The organization of a page-memory is shown in Figure 6. In contrast with the
first generation of Teletext Decoders the new CCT (Computer Controlled 
Teletext) chip provides a display format of 25 rows of 40 characters per row.
Row number twenty-four is used by the microprocessor for the display of 
information. Row zero contains the page header. The organization is as 
follows : The first seven characters (0 - 6) are used for messages regarding
the operational status. The eighth character is an alphanumeric control 
character either "white" or "green" defining the "search" status of the page.
When it is "white" the operational state is normal and the header appears 
white ; when it is "green" the operational state corresponds to "search mode"
and the header appears green. The following twenty-four characters give the
header of the requested page when the system is in search mode. The last eight
characters display the time of day. Row twenty-five comprises ten bytes of 
control data concerning the received page (see Table 1) and fourteen free 
bytes which can be used by the microprocessor.the SAA5231

REGISTER MAP (see Table 2)

Registers R1 to R10 are write only whilst R11 is a read/write register respect
to the microprocessor. The automatic succession on a byte basis is indicated 
by the arrows in Table 2. In the normal operating mode TA and TB should be set
to logic level 0. After power-up the contents of the registers are as follows:
all bits in registers R1 to R10 are cleared to zero with the exception of bits
D0 an D1 in registers R5 and R6 which are set to logical one. After power-up 
all the memory bytes are preset to hexadecimal value 20 H (space) with the 
exception of the byte corresponding to row 0 of column 7 of chapter 0 which is
set to the value corresponding to "alpha white" hexadecimal value 07 H.

 Table 1 : Row 25 received control data format
Ŀ   
 D0    PU0  PT0  MU0  MT0  HU0  HT0  C7   C11  MAG0   0    
Ĵ
 D1    PU1  PT1  MU1  MT1  HU1  HT1  C8   C12  MAG1   0    
Ĵ
 D2    PU2  PT2  MU2  MT2  HU2  C5   C9   C13  MAG2   0    
Ĵ
 D3    PU3  PT3  MU3  C4   HU3  C6   C10  C14  0      0    
Ĵ
 D4    HAM  HAM  HAM  HAM  HAM  HAM  HAM  HAM  FOUND  0    
Ĵ
 D5    0    0    0    0    0    0    0    0    0      PBLF 
Ĵ
 D6    0    0    0    0    0    0    0    0    0      0    
Ĵ
 D7    0    0    0    0    0    0    0    0    0      0    
Ĵ
COLUMN 0    1    2    3    4    5    6    7    8      9    

Page number   : MAG = magazine, PU = page units, PT = page tens.
Page sub-code : MU = minutes units, MT = minutes tens, 
                HU = hours units, HT = hours tens.
                PBLF = page being looked for, FOUND = low for page found,
                HAM = hamming error in byte, C4-14 = control bits.

 Table 2 : Register specification
Ŀ
 D7       D6         D5          D4         D3       D2        D1       D0      
Ĵ
 TA       7+P/8 BIT  ACQ.ON/OFF  GHOST ROW  DEW/FULL TCS ON    T1       T0       R1 Mode
                                 ENABLE     FIELD                               
Ĵ
 -        BANK       ACQ.        ACQ.       TB       START     START    START    R2 Page request adress
          SELECT     CCT         CCT                 COLUMN    COLUMN   COLUMN  
          A2         A1          A0                  SC2       SC1      SC0     
Ĵ
 -        -          -           PRD4       PRD3     PRD2      PRD1     PRD0     R3 Page request data
Ĵ
 -        -          -           -          -        A2        A1       A0       R4 Display chapter
Ĵ
 BKGND    BKGND      COR         COR        TEXT     TEXT      PON      PON      R5 Display control (normal)
 OUT      IN         OUT         IN         OUT      IN        OUT      IN      
Ĵ
 BKGND    BKGND      COR         COR        TEXT     TEXT      PON      PON      R6 Display control
 OUT      IN         OUT         IN         OUT      IN        OUT      IN       (newsflash / subtitle)
Ĵ
 STATUS   CURSOR     CONCEAL/    TOP/       SINGLE/  BOX ON    BOX ON   BOX ON   R7 Display mode
 ROW      ON         REVEAL      BOTTOM     DOUBLE     24       1-23      0     
 BTM/TOP                                    HEIGHT                              
Ĵ
 -        -          -           -          CLEAR     A2       A1       A0       R8 Active chapter
                                            MEM.                                
Ĵ
 -        -          -           R4         R3        R2       R1       R0       R9 Active row
Ĵ
 -        -          C5          C4         C3        C2       C1       C0       R10 Active column
Ĵ
 D7(R/W)  D6(R/W)    D5(R/W)     D4(R/W)    D3(R/W)   D2(R/W)  D1(R/W)  D0(R/W)  R11 Active data

  - bit does not exist.


 REGISTER FUNCTIONS
Ŀ
Register     Function              Bit(s)              Description                                        
Ĵ
                                T0,T1 (D0,D1)     These bits control the frame display format.Interlaced  
                                                  or non-interlaced,312/313 or 312/312.                   
                            Ĵ
                                TCS ON (D2)       This bit determines the character display               
                                                  synchronization mode. Teletext composite synchronism    
                                                  (TCS ON=1) or direct broadcast synchronism (TCS ON=0).  
                            Ĵ
   R1         Mode             DEW/FULLFIELD      Selection of field flyback mode or full channel mode    
            controls                (D3)          (D3 = 1) for recovering of Teletext data.               
                            Ĵ
                                 GHOST ROW        Selection of ghost row mode (D4 = 1)                    
                                ENABLE (D4)                                                               
                            Ĵ
                                ACQUISITION       Control of acquisition operation (D5 = 0 enables        
                                ON/OFF (D5)       acquisition)                                            
                            Ĵ
                            7 bits + parity or 8  Selection of received data format either 7 bits with    
                            bits without parity   parity (D6 = 0) or 8 bits without parity (D6 = 1).      
                                      (D6)                                                                
                            Ĵ
                                   TA (D7)        Test bit equal to "0" in the normal operating mode.     
Ĵ
   R2      Addressing            SC0,SC1,SC2      Address the first column of the on chip page request    
        information for           (D0,D1,D2)      RAM to be written.                                      
         a page request     Ĵ
                                   TB (D3)        Test bit equal to "0" in the normal working mode.       
                            Ĵ
                                A0,A1 (D4,D5)     Address a group of four consecutive pages currently     
                                                  used for data acquisition;                              
                            Ĵ
                                   A2 (D6)        Address of one of the two groups of four pages for      
                                                  acquisition in normal mode.                             
Ĵ
   R3   Data relative to the  PRD0-PRD4 (D0-D4)   Written data in the page request RAM, starting with the 
        requested page (see                       columns addressed by SC0,SC1,SC2.                       
           Table 3).                                                                                      
Ĵ
   R4   Selection of one of  A0,A1,A2 (D0,D1,D2)  These three bits correspond to the logical states of the
        eight pages to                            three address lines (A12,A11,A10) during memory read    
        display.                                  cycles.                                                 
Ĵ
   R5   Display control for    PON (D0,D1)        Picture on (IN: D0, OUT: D1)                            
        normal operation.   Ĵ
                               TEXT (D2,D3)       Text on (IN: D2, OUT: D3)                               
                            Ĵ
                                 COR (D4,D5)      Contrast reduction on (IN: D4, OUT: D5)                 
                                BKGND (D6,D7)     Background colour on (IN: D6, OUT: D7)                  
                                   IN/OUT         Enable inside/outside the box                           
Ĵ
   R6   Display control for        See R5         See R5                                                  
        news-flash subtitle                                                                               
        generation.                                                                                       
Ĵ
   R7      Display mode        BOX ON 0,1-23,24   The "boxing" function is enabled on row 0,1-23 and 24   
                                  (D0,D1,D2)      by D0, D1 and D2 set to one.                            
                            Ĵ
                                 STATUS ROW       The 25th row is displayed before the "Main text Area"   
                                BTM/TOP (D7)      (lines 0-23) or after (D7 = 0).                         
                                                                                                          
Ĵ
 R8-R11 Active chapter address (R8), active row address (R9), active column address (R10).                  
        Data contained in R11 read (written) from (to) memory by microprocessor via I2C bus.                



Table 3 : Register R3
Ŀ
START   PRD4                  PRD3  PRD2  PRD1  PRD0
COLUMN                                              
Ĵ
 0     Do care magazine       HOLD  MAG2  MAG1  MAG0
Ĵ
 1     Do care page tens      PT3   PT2   PT1   PT0 
Ĵ
 2     Do care page units     PU3   PU2   PU1   PU0 
Ĵ
 3     Do care hours tens      X     X    HT1   HT0 
Ĵ
 4     Do care hours units    HU3   HU2   HU1   HU0 
Ĵ
 5     Do care minutes tens    X    MT2   MT1   MT0 
Ĵ
 6     Do care minutes units  MU3   MU2   MU1   MU0 

 
The abbreviations have the same significance as in Table 1 with
the exception of the "DO CARE" entries. It is only when this bit
is "1" that the corresponding digit is taken into consideration
on page request. For example, a page defined as "normal" or one
difined as "timed" may be selected. If "HOLD" is low the page is
held. The addressing of successive bytes via the I2C bus is automatic


CHARACTER SETS

The complete character set with 8-bit decoding is given in Table 4.
Characters in columns 0 and 1 are normally displayed as blanks. Black
dots represent the character shape whereas white dots represent the background.
Each character can be identified by a pair of corresponding row and column
integers : for example the character "3" may be indicated by 3/3. A rectangle
may be represented as follows : The characters 8/6, 8/7, 9/5, 9/7 are used as
special characters, always in conjunction with 8/5. The 13 national characters
are placed in columns with bit 8 = 0.

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 Printed on 11/12/96 by Oleg Zilotin (AKA *ZiLeG*) 2:5020/758.8@FidoNet.Org
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